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VHDL supports processes 

 

•   Processes encapsulate a portion of a design

 

•   Processes have a sensitivity list that specifies signals and ports that cause changes in the outputs of the process

 

œ  Sensitivity lists can be used to preserve the state of a hardware system 

 

•   For example, an edge-triggered flip-flop circuit is sensitive to a particular clock edge

 

œ  The output of the edge-triggered flip-flop changes if and only if a particular clock edge is received

 

œ  Otherwise, the previous output remains asserted

The keywords used for conditional assignments and selected assignments differ from those used within a process:

 

 

 

Outside Processes  

Inside Processes  

WHEN..ELSE

IF..ELSIF..ELSE..END IF

WITH..SELECT..WHEN

CASE..WHEN..END CASE

 

 

 

 

•   A selected assignment outside a process is functionally equivalent to a case statement within a process

 

 

•   Processes can be used for combinational logic but most  often,  processes encapsulate sequential logic

 

 D flip flop withasynchronous active low reset signal

SIGNAL reset, clock, d, q :std_logic; PROCESS (reset, clock)

-- reset and clock are in the sensitivity list to

-- indicate that they are important inputs to the process

BEGIN

-- IF keyword is only valid in a process

IF (reset = ’0’) THEN

q <= 0;

ELSIF (clock’EVENT AND clock = ’1’) THEN
q <= d; END IF;
END PROCESS;
 

 

Following is an example of combinational circuit

PROCESS (a, b, d)

-- a, b, and d are in the sensitivity list to indicate that

-- the outputs of the process are sensitive to changes in them

BEGIN

-- CASE keyword is only valid in a process

CASE d IS

WHEN ‘0’ =>

c <= a AND b;
WHEN OTHERS =>

c <= ‘1’;

END CASE;
END PROCESS;




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