| VHDL Tutorial | Naming conventions | |||
|
Introduction to VHDL History of VHDL Naming Conventions Libraries and packages Entities Entity Declaration Entity Example Ports Architectures Architecture declaration Architecture example Configurations Signals Signal representation Multivalued logic representation Built in data types Synthesis vs simulation Logical operators Assignment statements Process statements D Flip flop example code Finite state machine(FSM) Finite state machine example Combinational circuit example code Quad 2 input MUX example Seven segment display controller 8 Bit register 32 bit counter
|
For the purpose of this tutorial, the following naming conventions will be used:
œ All VHDL keywords are shown in uppercase
œ All identifiers are shown in lowercase
œ The color highlighting used by Altera Quartus II has been used to enhance the readability of the VHDL code fragments
• In general, you should consult the style guide for your tools
œ Most (if not all tools) provide a VHDL coding style guide with style recommendations
œ Most companies implement a VHDL coding style to improve the readability of hardware designs
Want To Know more with Video ??? Contact for more learning: webmaster@freehost7com
|
|