VHDL Tutorial Naming conventions
Introduction to VHDL
History of VHDL
Naming Conventions

Libraries and packages
Entity Declaration
Entity Example
Architecture declaration
Architecture example
Signal representation
Multivalued logic representation
Built in data types
Synthesis vs simulation
Logical operators
Assignment statements
Process statements
D Flip flop example code
Finite state machine(FSM)
Finite state machine example
Combinational circuit example code
Quad 2 input MUX example
Seven segment display controller
8 Bit register
32 bit counter







For the purpose of this tutorial, the following naming  conventions will be used:


  All VHDL keywords are shown in uppercase


  All identifiers are shown in lowercase


  The color highlighting used by Altera Quartus II has been used to enhance the readability of the VHDL code fragments



   In general, you should consult the style guide for your tools


  Most (if not all tools) provide a VHDL coding style guide with style recommendations


  Most companies implement a VHDL coding style to improve the readability of hardware designs


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