History of VHDL
Naming Conventions
Libraries and packages
Entities
Entity Declaration
Entity Example
Ports
Architectures
Architecture declaration
Architecture example
Configurations
Signals
Signal representation
Multivalued logic representation
Built in data types
Synthesis vs simulation
Logical operators
Assignment statements
Process statements
D Flip flop example code
Finite state machine(FSM)
Finite state machine example
Combinational circuit example code
Quad 2 input MUX example
Seven segment display controller
8 Bit register
32 bit counter
Design a VHDL entity named andnand to specify the interface
of the following circuit:
• Use std_logic for the port signal types of all input and output pins
The VHDL description of the andnand entity should resemble the following:
Another Example :
Design a VHDL architecture to specify the internal implementation of andnand
• Name the architecture synthesis1
The VHDL description of the andnand architecture should resemble the following:
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