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Introduction to VHDL History of VHDL Naming Conventions Libraries and packages Entities Entity Declaration Entity Example Ports Architectures Architecture declaration Architecture example Configurations Signals Signal representation Multivalued logic representation Built in data types Synthesis vs simulation Logical operators Assignment statements Process statements D Flip flop example code Finite state machine(FSM) Finite state machine example Combinational circuit example code Quad 2 input MUX example Seven segment display controller 8 Bit register 32 bit counter
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SIGNAL a, b, c : std_logic;
SIGNAL avec, bvec, cvec : std_logic_vector(7 DOWNTO 0);
-- Concurrent Signal Assignment Statements
-- NOTE: Both a and avec are produced concurrently
a <= b AND c;
avec <= bvec OR cvec;
-- Alternatively, signals may be assigned constants
SIGNAL a, b, c, d :std_logic;
-- Conditional Assignment Statement -- NOTE: This implements a tree structure of logic gates
c WHEN d = ’1’ ELSE ’1’;
-- Selected Signal Assignment Statement -- NOTE: The selection values must be constants bvec <= d & avec; WITH bvec SELECT a <= ’0’ WHEN “000”, b WHEN “011”, c WHEN “1--”, -- Some tools won’t synthesize ‘-’ properly ’1’ WHEN OTHERS;
-- Selected Signal Assignment Statement
-- NOTE: Selected signal assignments also work
-- with vectors
WITH a SELECT
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