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SIGNAL a, b, c             : std_logic;

 

SIGNAL avec, bvec, cvec     : std_logic_vector(7 DOWNTO 0);

 

 

 

-- Concurrent Signal Assignment Statements

 

-- NOTE: Both a and avec are produced concurrently

 

a        <= b AND c;

 

avec     <= bvec OR cvec;

 

 

 

-- Alternatively, signals may be assigned constants

 

a

<=

0;

 

 

 

 

 

b

<=

1;

 

 

 

 

 

c

<=

Z;

 

 

 

 

 

avec

<=

"00111010";

--

Assigns

0x3A

to

avec

bvec

<=

X"3A";

--

Assigns

0x3A

to

bvec

cvec

<=

X"3" & X"A";

--

Assigns

0x3A

to

cvec

SIGNAL a, b, c, d          :std_logic;

SIGNAL

avec

:std_logic_vector(1

DOWNTO

0);

SIGNAL

bvec

:std_logic_vector(2

DOWNTO

0);

 

 

-- Conditional Assignment Statement

-- NOTE: This implements a tree structure of logic gates

a

<=

0

WHEN

avec

=

00

ELSE

 

 

b

WHEN

avec

=

11

ELSE

 

c        WHEN d = 1 ELSE

1;

 

 

-- Selected Signal Assignment Statement

-- NOTE: The selection values must be constants bvec <= d & avec;

WITH bvec SELECT

a <=     0        WHEN 000, b        WHEN 011,

c        WHEN 1--,       -- Some tools wont synthesize - properly

1      WHEN OTHERS;

 

 

 

 

SIGNAL

 

 

a

 

 

 

:std_logic;

 

 

SIGNAL

avec,

bvec

:std_logic_vector(7

DOWNTO

0);

 

 

 

-- Selected Signal Assignment Statement

 

-- NOTE: Selected signal assignments also work

 

--       with vectors

 

WITH a SELECT

 

avec

<=

01010101

WHEN

1,

 

 

bvec

WHEN

OTHERS;

 

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