| VHDL Tutorial | Architecture declaration example | |||
|
Introduction to VHDL History of VHDL Naming Conventions Libraries and packages Entities Entity Declaration Entity Example Ports Architectures Architecture declaration Architecture example Configurations Signals Signal representation Multivalued logic representation Built in data types Synthesis vs simulation Logical operators Assignment statements Process statements D Flip flop example code Finite state machine(FSM) Finite state machine example Combinational circuit example code Quad 2 input MUX example Seven segment display controller 8 Bit register 32 bit counter
|
The following is an example of an architecture declaration for an AND gate: ARCHITECTURE synthesis1 OF andgate IS BEGIN
c<=a AND b;
END synthesis1;
Want To Know more with Video ??? Contact for more learning: webmaster@freehost7com
|
|