VHDLTutorial 8 bit Register
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8 Bit register

32 bit counter
 
 
 
 
 

 

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Design a synthesizable VHDL specification of a 8-bit register with an enable signal and an asynchronous reset signal

 

 

•   The block diagram of the 8-bit register is shown below:

 

 

 

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;


ENTITY dregister IS
PORT( rst, clk, ena : IN std_logic;
d : IN std_logic_vector(7 DOWNTO 0);
q : OUT std_logic_vector(7 DOWNTO 0) ); END dregister;


ARCHITECTURE synthesis1 OF dregister IS BEGIN
PROCESS (rst, clk) BEGIN
IF (rst = ‘1’) THEN
q <= X”00”;
ELSIF (clk’EVENT) AND (clk = ‘1’) THEN IF (ena = ‘1’) THEN
q <= d;



END IF;
END PROCESS;
END synthesis1;

END IF;
 

 

 


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