HOME
 

Design a synthesizable VHDL implementation of a 32-bit counter with an enable signal and an asynchronous reset signal

•   The block diagram of the 32-bit counter is shown below:

 LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;


ENTITY counter IS PORT(
reset : IN std_logic;
clock : IN std_logic;
enable : IN std_logic;
value : OUT std_logic_vector(31 DOWNTO 0)
);
END counter;
 

ARCHITECTURE synthesis1 OF counter IS


-- The unsigned type is used
SIGNAL count : unsigned(31 DOWNTO 0); -- so that unsigned arithmetic
-- will be synthesized


BEGIN
PROCESS (reset, clock) BEGIN
IF (reset = ‘1’) THEN
count <= X”00000000”;
ELSIF (clock’EVENT) AND (clock = ‘1’) THEN IF (enable = ‘1’) THEN
count <= count + 1;



END IF; END PROCESS;

END IF;






-- Here, the count value is

value <= std_logic_vector(count); -- converted to std_logic_vector
-- using a conversion function


END synthesis1;

 

Want To Know more with

Video ???

Contact for more learning: webmaster@freehost7com

Home