|Standard logic in VHDL|
The IEEE has standardized a package called std_logic_1164 that allows us to model digital signals taking into account some electrical effects. One of the types defined in this package is an enumeration type called std_ulogic, defined as
type std_ulogic is ( 'U', Uninitialized
'X', Forcing Unknown
'0', Forcing zero
'1', Forcing one
'Z', High Impedance
'W', Weak Unknown
'L', Weak zero
'H', Weak one
'' ); Don't care
Want To have highly paid VLSI jobs ?? then you may contact at Contact : webmaster@freehost7com
Want To have highly paid VLSI jobs ?? then you may contact at
Contact : webmaster@freehost7com
This type can be used to represent signals driven by active drivers (forcing strength), resistive drivers such as pull-ups and pull-downs (weak strength) or three- state drivers including a high-impedance state. Each kind of driver may drive a zero,
one or unknown value. An unknown value is driven by a model when it is un- able to determine whether the signal should be zero or one. In addition to these values, the leftmost value in the type represents an uninitialized value. If we declare signals of std_ulogic type, by default they take on U as their initial value. The final value in std_ulogic is a dont care value. This is sometimes used by logic synthesis tools and may also be used when defining test vectors, to denote that the value of a signal to be compared with a test vector is not important.
Even though the type std_ulogic and the other types defined in the std_logic_1164 package are not actually built into the VHDL language, we can write models as though they were, with a little bit of preparation. For now, we describe some magic to include at the beginning of a model that uses the package; we explain the details later.
If we include the line
library ieee; use ieee.std_logic_1164.all;
preceding each entity or architecture body that uses the package, we can write models as though the types were built into the language.
With this preparation in hand, we can now create constants, variables and signals
of type std_ulogic. As well as assigning values of the type, we can also use the logical operators and, or, not and so on. Each of these operates on std_ulogic values and returns a std_ulogic result of U, X, 0 or 1.