|Signal Parameters in VHDL|
Elements of behaviour
Elements of structure
Characters and strings
Constants and variables
Floating point types
Loop and exit statements
Array types & array operations
Conditional signal assignment
Selected signal assigment
Library and library clauses
Unconstrained array parameter
Package declarations and bodies
Subprograms in package
Resolved signals and subtypes
Resolved signals and ports
The third class of object that we can specify for formal parameters is signal, which indicates that the algorithm performed by the procedure involves a signal passed by the caller. A signal parameter can be of any of the modes in, out or inout.
The way that signal parameters work is somewhat different from constant and variable parameters. When a caller passes a signal as a parameter of mode in, instead
of passing the value of the signal, it passes the signal object itself. Any reference to the formal parameter within the procedure is exactly like a reference to the actual sig- nal itself.
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Suppose we wish to model the receiver part of a network interface. It re- ceives fixed-length packets of data on the signal rx_data. The data is synchronized with changes, from ‘0’ to ‘1’, of the clock signal rx_clock. Figure 5-4 is an outline
of part of the model.
architecture behavioral of receiver is
… – – type declarations, etc
signal recovered_data : bit;
signal recovered_clock : bit;
procedure receive_packet ( signal rx_data : in bit;
signal rx_clock : in bit;
data_buffer : out packet_array ) is
for index in packet_index_range loop wait until rx_clock = '1'; data_buffer(index) := rx_data;
end procedure receive_packet;
packet_assembler : process is variable packet : packet_array;
receive_packet ( recovered_data, recovered_clock, packet );
end process packet_assembler;
end architecture behavioral;
An outline of a model of a network receiver, including a procedure with signal parameters of mode in.
During execution of the model, the process packet_assembler calls the proce- dure receive_packet, passing the signals recovered_data and recovered_clock as ac- tual parameters. The wait statement mentions rx_clock, and since this stands for recovered_clock, the process is sensitive to changes on recovered_clock while it is
Now let’s look at signal parameters of mode out. In this case, the caller must name a signal as the actual parameter, and the procedure is passed a reference to the driver for the signal. When the procedure performs a signal assignment statement on the formal parameter, the transactions are scheduled on the driver for the actual signal parameter.
Figure 5-5 is an outline of an architecture body for a signal generator. The procedure generate_pulse_train has in mode constant parameters that specify the characteristics of a pulse train and an out mode signal parameter on which it gen- erates the required pulse train. The process raw_signal_generator calls the procedure, supplying raw_signal as the actual signal parameter for s. A reference to the driver for raw_signal is passed to the procedure, and transactions are generated on it.
library ieee; use ieee.std_logic_1164.all;
architecture top_level of signal_generator is signal raw_signal : std_ulogic;
procedure generate_pulse_train ( width, separation : in delay_length;
number : in natural;
signal s : out std_ulogic ) is
for count in 1 to number loop
s <= '1', '0' after width;
wait for width + separation;
end procedure generate_pulse_train;
raw_signal_generator : process is begin
generate_pulse_train ( width => period / 2,
separation => period – period / 2, number => pulse_count,
s => raw_signal );
end process raw_signal_generator;
end architecture top_level;
An outline of a model for a signal generator, including a pulse generator procedure with an out mode
As with variable-class parameters, we can also have a signal-class parameter of mode inout. When the procedure is called, both the signal and a reference to its driver are passed to the procedure. The statements within it can read the signal value, in- clude it in sensitivity lists in wait statements, query its attributes and schedule trans- actions using signal assignment statements.