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VHDL Tutorial |
Selected signal assigment statements in VHDL | |||||||||||||||||
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Selected Signal Assignment Statements
The selected signal assignment statement is similar in many ways to the conditional signal assignment statement. It is a shorthand for a process containing a number of ordinary signal assignments within a case statement. The syntax rule is
selected_signal_assignment ⇐ with expression select name <= { waveform when choices , } waveform when choices ;
This statement allows us to choose between a number of waveforms to be as- signed to a signal depending on the value of an expression. An example is:
with alu_function select
A selected signal assignment statement is sensitive to all of the signals in the se- lector expression and in the expressions on the right of the assignment arrow. This means that the selected signal assignment above is sensitive to alu_function, a and b.
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