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Resolved signals and subtypes in VHDL
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Resolved signals and subtypes

Resolved signals and ports
Parameterizing behavior
Parameterizing structure

IEEE Std_Logic_1164 Resolved Subtypes

 

VHDL provides a very general mechanism for specifying what value results from con- necting multiple outputs together.  It does this through resolved subtypes and resolved signals, which are an extension of the basic signals we have used in previous chap- ters However,  most  designs  simply  use  the  resolved  subtypes  defined  in  the  stan- dard-logic  package,  std_logic_1164 In  this  tutorial,  we  will  restrict  our  attention  to those subtypes.

First, recall that the package provides the basic type std_ulogic, defined as

 

type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '–');

 

and an array type std_ulogic_vector, defined as

 

type std_ulogic_vector is array ( natural range <> ) of std_ulogic;

 

We have not mentioned it before, but the “u” in “ulogic” stands for unresolved. Signals of these types cannot have multiple sources.  The standard-logic package also provides a resolved subtype called std_logic.  A signals of this type can have multiple sources.   The package also declares an array type of standard-logic elements, analo- gous to the bit_vector type, for use in declaring array signals:

 

type std_logic_vector is array ( natural range <>) of std_logic;

 

The  standard  defines  the  way  in  which  contributions  from  multiple  sources  are resolved to yield the final value for a signal.   If there is only one driving value, that value is used. If one driver of a resolved signal drives a forcing value (‘X’, ‘0’ or ‘1’) and another drives a weak value(‘W’, ‘L’ r ‘H’), the forcing value dominates.   On the other hand, if both drivers drive different values with the same strength, the result is the  unknown  value  of  that  strength  (‘X’  or  ‘W’).   The  high-impedance  value,  ‘Z’,  is dominated by forcing and weak values.   If a “don’t care” value –’) is resolved with any other value, the result is the unknown value ‘X’.  The interpretation of the “don’t care” value is that the model has not made a choice about its output state.  Finally, if an “uninitialize value (‘U’) is to be resolved with any other value, the result is ‘U’, indicating that the model has not properly initialized all outputs.

In addition to this multivalued logic subtype, the package std_logic_1164 declares

a number of subtypes for more restricted multivalued logic modeling.   The subtype declarations are

 

subtype X01 is resolved std_ulogic range 'X' to '1';        – – ('X','0','1') subtype X01Z is resolved std_ulogic range 'X' to 'Z';                                     – – ('X','0','1','Z') subtype UX01 is resolved std_ulogic range 'U' to '1';                                     – – ('U','X','0','1') subtype UX01Z is resolved std_ulogic range 'U' to 'Z';                                     – – ('U','X','0','1','Z')

 

The standard-logic package provides the logical operators and, nand, or, nor, xor,

xnor and not for standard-logic values and vectors, returning values in the range ‘U’,

‘X’,  ‘0’  or  ‘1’.   In  addition,  there  are  functions  to  convert  between  values  of  the  full standard-logic type, the subtypes shown above and the predefined bit and bit-vector types.

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