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VHDL Tutorial |
Process Statements in VHDL | ||
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Introduction Fundamental concepts Modelling concepts Elements of behaviour Elements of structure Analysis elaboration Lexical elements Identifiers Numbers Characters and strings Syntax descriptions Constants and variables Scalar type Integer types Floating point types Time type Enumeration types Character types Boolean type Bits type Standard logic Sequential statements Case statements Loop and exit statements Assertion statements Array types & array operations Architecture bodies Entity declarations Behavioral descriptions Wait statements Delta delays Process statements Conditional signal assignment Selected signal assigment Structural descriptions Library and library clauses Procedures Procedure parameters Signal parameters Default values Unconstrained array parameter Functions Package declarations and bodies Subprograms in package Use clauses Resolved signals and subtypes Resolved signals and ports Parameterizing behavior Parameterizing structure |
Process Statements
We have been using processes quite extensively in examples in this and previous chapters, so we have seen most of the details of how they are written and used. To summarize, let us now look at the formal syntax for a process statement and review process operation. The syntax rule is
process_statement ⇐ process_label : process [ ( signal_name { , … } ) ] [ is ] { process_declarative_item } begin { sequential_statement } end process [ process_label ] ;
The declarative items in a process statement may include constant, type and vari- able declarations, as well as other declarations that we will come to later. The se- quential statements that form the process body may include any of those that we introduced earlier, plus signal assignment and wait statements. When a process is ac- tivated during simulation, it starts executing from the first sequential statement and continues until it reaches the last. It then starts again from the first. This would be an infinite loop, with no progress being made in the simulation, if it were not for the inclusion of wait statements, which suspend process execution until some relevant event occurs. Wait statements are the only statements that take more than zero sim- ulation time to execute. It is only through the execution of wait statements that sim- ulation time advances.
A process may include a sensitivity list in parentheses after the keyword process. The sensitivity list identifies a set of signals that the process monitors for events. If the sensitivity list is omitted, the process should include one or more wait statements. On the other hand, if the sensitivity list is included, then the process body cannot in- clude any wait statements. Instead, there is an implicit wait statement, just before the end process keywords, that includes the signals listed in the sensitivity list as signals in an on clause.
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