VHDL Tutorial

Library and Library Clauses
Introduction
Fundamental concepts
Modelling concepts
Elements of behaviour
Elements of structure
Analysis elaboration
Lexical elements
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Scalar type
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Architecture bodies
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Behavioral descriptions 
Wait statements
Delta delays
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Conditional signal assignment 
Selected signal assigment
Structural descriptions
Library and library clauses

Procedures
Procedure parameters
Signal parameters
Default values
Unconstrained array parameter
Functions
Package declarations and bodies
Subprograms in package
Use clauses
Resolved signals and subtypes
Resolved signals and ports
Parameterizing behavior
Parameterizing structure

Libraries and Library Clauses

 

Earlier, we mentioned that a design is analyzed in order to check that it conforms to the syntax and semantic rules of VHDL.   An analyzed design unit, such as an entity declaration or architecture body, is placed  into a design library.   A VHDL tool suite must  provide  some  means  of  using  a  number  of  separate  design  libraries.   When  a design is analyzed, we nominate one of the libraries as the working library, and the analyzed design is stored in this library.  We use the special library name work in our VHDL models to refer to the current working library.  We have seen examples of this

in this chapter’s component instantiation statements, in which a previously analyzed entity is instantiated in a structural architecture body.

If we need to access library units stored in other libraries, we refer to the libraries

as resource libraries.  We do this by including a library clause immediately preceding

a design unit that accesses the resource libraries.  The syntax rule for a library clause is library_clause library identifier { , } ;

The identifiers are used by the analyzer and the host operating system to locate the design libraries, so that the units contained in them can be used in the description being analyzed.   The exact way that the identifiers are used varies between different tool suites and is not defined by the VHDL language specification Note that we do not need to include the library name work in a library clause; the current working li- brary is automatically available.

 

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EXAMPLE

 

Suppose we are working on part of a large design project code-named Wasp, and we are using standard cell parts supplied by Widget Designs, Inc.  Our system administrator  has  loaded  the  design  library  for  the  Widget  cells  in  a  directory called  /local/widget/cells  in  our  workstation  file  system,  and  our  project  leader has set up another design library in /projects/wasp/lib for some in-house cells we need to use.   We consult the manual for our VHDL analyzer and use operating system   commands   to   set   up   the   appropriate   mapping   from   the   identifiers widget_cells and wasp_lib to these library directories.   We can then instantiate en- tities from  these libraries,  along with  entities  we have previously  analyzed,  into our own working library, as shown in Figure 4-6.

FIGURE 4-6

 

library widget_cells, wasp_lib;

architecture cell_based of filter is

– declaration of signals, etc

begin

clk_pad : entity wasp_lib.in_pad

port map ( i => clk, z => filter_clk );

accum : entity widget_cells.reg32

port map ( en => accum_en, clk => filter_clk, d => sum, q => result );

alu : entity work.adder

port map ( a => alu_op1, b => alu_op2, y => sum, c => carry );

– other component instantiations

end architecture cell_based;

 

An outline of a library unit referring to entities from the resource libraries widget_cells and wasp_lib.

 

 

 

 

 

 

 

 

 

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