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Generic constants Parameterizing Structure | ||
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Parameterizing Structure
The second main use of generic constants in entities is to parameterize their structure. We can use the value of a generic constant to specify the size of an array port by using the generic constant in constraints in the port declarations. To illustrate, here is an entity declaration for a register:
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Contact : webmaster@freehost7com entity reg is generic ( width : positive );
port ( d : in bit_vector(0 to width – 1); q : out bit_vector(0 to width – 1); … ); end entity reg;
In this declaration we require that the user of the register specify the desired port width for each instance. The entity then uses the width value as a constraint on both the input and output ports. A component instantiation using this entity might appear as follows:
signal in_data, out_data : bit_vector(0 to bus_size – 1); … ok_reg : entity work.reg generic map ( width => bus_size ) port map ( d => in_data, q => out_data, … );
A complete model for the register, including the entity declaration and an ar- chitecture body, is shown in Figure 8-1. The generic constant is used to constrain the widths of the data input and output ports in the entity declaration. It is also used in the architecture body to determine the size of the constant bit vector zero. This bit vector is the value assigned to the register output when it is reset, so it must be of the same size as the register port. We can create instances of the register entity in a design, each possibly having different-sized ports. For example:
word_reg : entity work.reg(behavioral) generic map ( width => 32 ) port map ( … );
creates an instance with 32-bit-wide ports. In the same design, we might include another instance, as follows:
subtype state_vector is bit_vector(1 to 5); … state_reg : entity work.reg(behavioral) generic map ( width => state_vector'length ) port map ( … );
This register instance has 5-bit-wide ports, wide enough to store values of the sub- type state_vector.
entity reg is generic ( width : positive ); port ( d : in bit_vector(0 to width – 1); q : out bit_vector(0 to width – 1); clk, reset : in bit ); end entity reg; architecture behavioral of reg is begin behavior : process (clk, reset) is constant zero : bit_vector(0 to width – 1) := (others => '0'); begin if reset = '1' then q <= zero; elsif clk'event and clk = '1' then q <= d; end if; end process behavior;
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