|
VHDL Tutorial |
Entity Declarations in VHDL | ||
|
Introduction Fundamental concepts Modelling concepts Elements of behaviour Elements of structure Analysis elaboration Lexical elements Identifiers Numbers Characters and strings Syntax descriptions Constants and variables Scalar type Integer types Floating point types Time type Enumeration types Character types Boolean type Bits type Standard logic Sequential statements Case statements Loop and exit statements Assertion statements Array types & array operations Architecture bodies Entity declarations Behavioral descriptions Wait statements Delta delays Process statements Conditional signal assignment Selected signal assigment Structural descriptions Library and library clauses Procedures Procedure parameters Signal parameters Default values Unconstrained array parameter Functions Package declarations and bodies Subprograms in package Use clauses Resolved signals and subtypes Resolved signals and ports Parameterizing behavior Parameterizing structure
|
Entity Declarations
Let us first examine the syntax rules for an entity declaration and then show some ex- amples. The syntax rules are
Want To have highly paid VLSI jobs ?? then you may contact at
Contact : webmaster@freehost7com entity_declaration ⇐ entity identifier is [ port ( port_interface_list ) ; ] end [ entity ] [ identifier ] ; interface_list ⇐ ( identifier { , … } : [ mode ] subtype_indication ) { ; … } mode ⇐ in I out I inout
The identifier in an entity declaration names the module so that it can be referred to later. If the identifier is included at the end of the declaration, it must repeat the name of the entity. The port clause names each of the ports, which together form the interface to the entity. We can think of ports as being analogous to the pins of a cir- cuit; they are the means by which information is fed into and out of the circuit. In VHDL, each port of an entity has a type, which specifies the kind of information that can be communicated, and a mode, which specifies whether information flows into or out from the entity through the port. A simple example of an entity declaration is
entity adder is port ( a, b : in word; sum : out word ); end entity adder;
This example describes an entity named adder, with two input ports and one out- put port, all of type word, which we assume is defined elsewhere. We can list the ports in any order; we do not have to put inputs before outputs. In this example we have input and output ports. We can also have bidirectional ports, with mode inout, to model devices that alternately sense and drive data through a pin. Such models must deal with the possibility of more than one connected device driving a given signal at the same time. VHDL provides a mechanism for this, signal resolution, which we will return to later. Note that the port clause is optional. So we can write an entity declaration such as entity top_level is end entity top_level;
which describes a completely self-contained module. As the name in this example implies, this kind of module usually represents the top level of a design hierarchy.
|