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VHDL Tutorial |
Elements of structure and test benches | ||
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Introduction Fundamental concepts Modelling concepts Elements of behaviour Elements of structure Analysis elaboration Lexical elements Identifiers Numbers Characters and strings Syntax descriptions Constants and variables Scalar type Integer types Floating point types Time type Enumeration types Character types Boolean type Bits type Standard logic Sequential statements Case statements Loop and exit statements Assertion statements Array types & array operations Architecture bodies Entity declarations Behavioral descriptions Wait statements Delta delays Process statements Conditional signal assignment Selected signal assigment Structural descriptions Library and library clauses Procedures Procedure parameters Signal parameters Default values Unconstrained array parameter Functions Package declarations and bodies Subprograms in package Use clauses Resolved signals and subtypes Resolved signals and ports Parameterizing behavior Parameterizing structure |
. Elements of Structure
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An architecture body that is composed only of interconnected subsystems is called a structural architecture body. Figure 2-4 shows how the reg4 entity might be com- posed of D-flipflops. If we are to describe this in VHDL, we will need entity declara- tions and architecture bodies for the subsystems, shown in Figure 2-5. Figure 2-6 is a VHDL architecture body declaration that describes the structure shown in Figure 2-4. The signal declaration, before the keyword begin, defines the internal signals of the architecture. In this example, the signal int_clk is declared to carry a bit value (‘0’ or ‘1’). In general, VHDL signals can be declared to carry arbi- trarily complex values. Within the architecture body the ports of the entity are also treated as signals. In the second part of the architecture body, a number of component instances are created, representing the subsystems from which the reg4 entity is composed. Each component instance is a copy of the entity representing the subsystem, using the cor- responding basic architecture body. (The name work refers to the current working li- brary, in which all of the entity and architecture body descriptions are assumed to be held.) The port map specifies the connection of the ports of each component instance to signals within the enclosing architecture body. For example, bit0, an instance of the d_ff entity, has its port d connected to the signal d0, its port clk connected to the signal int_clk and its port q connected to the signal q0.
Test Benches
We often test a VHDL model using an enclosing model called a test bench. The name comes from the analogy with a real hardware test bench, on which a device under test is stimulated with signal generators and observed with signal probes. A VHDL test bench consists of an architecture body containing an instance of the component to be tested and processes that generate sequences of values on signals connected to the component instance. The architecture body may also contain processes that test that the component instance produces the expected values on its output signals. Al- ternatively, we may use the monitoring facilities of a simulator to observe the outputs.
FIGURE 2-4
entity d_ff is port ( d, clk : in bit; q : out bit ); end d_ff; architecture basic of d_ff is begin ff_behavior : process is begin wait until clk = '1'; q <= d after 2 ns; end process ff_behavior; end architecture basic; –– ––– –––– ––– –––– –––– ––– –––– ––– –––– ––– –––– –––– ––– –––– entity and2 is port ( a, b : in bit; y : out bit ); end and2;
architecture basic of and2 is begin and2_behavior : process is begin y <= a and b after 2 ns; wait on a, b; end process and2_behavior;
architecture struct of reg4 is signal int_clk : bit; begin bit0 : entity work.d_ff(basic) port map (d0, int_clk, q0); bit1 : entity work.d_ff(basic) port map (d1, int_clk, q1); bit2 : entity work.d_ff(basic) port map (d2, int_clk, q2); bit3 : entity work.d_ff(basic) port map (d3, int_clk, q3); gate : entity work.and2(basic) port map (en, clk, int_clk); end architecture struct;
A test bench model for the behavioral implementation of the reg4 register is shown in Figure 2-7. The entity declaration has no port list, since the test bench is entirely self-contained. The architecture body contains signals that are connected to the input and output ports of the component instance dut, the device under test. The process labeled stimulus provides a sequence of test values on the input signals by performing signal assignment statements, interspersed with wait statements. We can use a simulator to observe the values on the signals q0 to q3 to verify that the register operates correctly. When all of the stimulus values have been applied, the stimulus process waits indefinitely, thus completing the simulation.
entity test_bench is end entity test_bench; architecture test_reg4 of test_bench is signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit; begin dut : entity work.reg4(behav) port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 ); stimulus : process is begin d0 <= '1'; d1 <= '1'; d2 <= '1'; d3 <= '1'; en <= '0'; clk <= '0'; wait for 10 ns; en <= '1'; wait for 10 ns; clk = '1', '0' after 10 ns; wait for 20 ns; d0 <= '0'; d1 <= '0'; d2 <= '0'; d3 <= '0'; en <= '0'; wait for 10 ns; clk <= '1', '0' after 10 ns; wait for 20 ns; … wait; end process stimulus; end architecture test_reg4;
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