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VHDL Tutorial |
Elements of behaviour | ||
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Introduction |
. Elements of Behavior
In VHDL, a description of the internal implementation of an entity is called an archi- tecture body of the entity. There may be a number of different architecture bodies of the one interface to an entity, corresponding to alternative implementations that per- form the same function. We can write a behavioral architecture body of an entity, which describes the function in an abstract way. Such an architecture body includes only process statements, which are collections of actions to be executed in sequence. These actions are called sequential statements and are much like the kinds of state- ments we see in a conventional programming language. The types of actions that can be performed include evaluating expressions, assigning values to variables, condition- al execution, repeated execution and subprogram calls. In addition, there is a sequen- tial statement that is unique to hardware modeling languages, the signal assignment statement. This is similar to variable assignment, except that it causes the value on a signal to be updated at some future time. To illustrate these ideas, let us look at a behavioral architecture body for the reg4 entity, shown in Figure 2-3. In this architecture body, the part after the first begin key- word includes one process statement, which describes how the register behaves. It starts with the process name, storage, and finishes with the keywords end process.
architecture behav of reg4 is begin storage : process is variable stored_d0, stored_d1, stored_d2, stored_d3 : bit; begin wait until clk = '1'; if en = '1' then stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3; end if; q0 <= stored_d0 after 5 ns; q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns; end process storage; end architecture behav;
The process statement defines a sequence of actions that are to take place when the system is simulated. These actions control how the values on the entity’s ports change over time; that is, they control the behavior of the entity. This process can modify the values of the entity’s ports using signal assignment statements. The way this process works is as follows. When the simulation is started, the sig- nal values are set to ‘0’, and the process is activated. The process’s variables (listed after the keyword variable) are initialized to ‘0’, then the statements are executed in order. The first statement is a wait statement that causes the process to suspend. Whil the process is suspended, it is sensitive to the clk signal. When clk changes value to ‘1’, the process resumes. The next statement is a condition that tests whether the en signal is ‘1’. If it is, the statements between the keywords then and end if are executed, updating the pro- cess’s variables using the values on the input signals. After the conditional if state- ment, there are four signal assignment statements that cause the output signals to be updated 5 ns later. When the process reaches the end of the list of statements, they are executed again, starting from the keyword begin, and the cycle repeats. Notice that while the process is suspended, the values in the process’s variables are not lost. This is how the process can represent the state of a system.
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