VHDL Tutorial

Constants and variables in VHDL
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Constants and variables

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Constants and Variables

 

Constants and variables are objects in which data can be stored for use in a model. The difference between them is that the value of a constant cannot be changed after

it is created, whereas a variables value can be changed as many times as necessary using variable assignment statements.

Both  constants  and  variables need  to be  declared  before  they  can  be  used  in  a model A declaration simply introduces the name of the object, defines its type and may give it an initial value.   The syntax rule for a constant declaration is

 

constant_declaration

constant identifier { , } : subtype_indication := expression ;

 

 

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Here are some examples of constant declarations:

 

constant number_of_bytes : integer := 4;

constant number_of_bits : integer := 8 * number_of_bytes;

constant e : real := 2.718281828;

constant prop_delay : time := 3 ns;

constant size_limit, count_limit : integer := 255;

 

The form of a variable declaration is similar to a constant declaration.  The syntax rule is

 

variable_declaration

variable identifier { , } : subtype_indication [ := expression ] ;

 

The initialization expression is optional; if we omit it, the default initial value as- sumed by the variable when it is created depends on the type.   For scalar types, the default initial value is the leftmost value of the type For example, for integers it is the smallest representable integer.   Some examples of variable declarations are

 

variable index : integer := 0;

variable sum, average, largest : real;

variable start, finish : time := 0 ns;

 

Constant and variable declarations can appear in a number of places in a VHDL model, including in the declaration parts of processes.  In this case, the declared object can be used only within the process.  One restriction on where a variable declaration may  occur  is  that  it  may  not  be  placed  so  that  the  variable  would  be  accessible  to

more  than  one  process.   This  is  to  prevent  the  strange  effects  that  might  otherwise occur if the processes were to modify the variable in indeterminate order.

Once a variable has been declared, its value can be modified by an assignment state- ment.   The syntax of a variable assignment statement is given by the rule

 

variable_assignment_statement name := expression ;

 

The  name  in  a  variable  assignment  statement  identifies  the  variable  to  be changed, and the expression is evaluated to produce the new value.  The type of this value must  match the  type  of  the variable.   Here  are some  examples of  assignment statements:

 

program_counter := 0;

index := index + 1;

 

The first assignment sets the value of the variable program_counter to zero, overwriting any previous value.   The second example increments the value of index by one.

 

 

 

 

 

 

 

 

 

 

 

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