VHDL Tutorial

Conditional signal assignment statements in VHDL
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Conditional Signal Assignment Statements

 

The conditional signal assignment statement is a concurrent statement that is a short- hand for a process containing a collection of ordinary signal assignments within an if statement.   The syntax rule is

 

conditional_signal_assignment

name <= { waveform when boolean_expression else }

waveform [ when boolean_expression ] ;

 

The  conditional  signal  assignment  allows  us  to  specify  which  of  a  number  of waveforms  should  be  assigned  to  a signal  depending  on  the  values  of  some  condi- tions.  For example, the following statement is a functional description of a multiplex- er, with four data inputs (d0, d1, d2 and d3), two select inputs (sel0 and sel1) and a data output (z).   All of these signals are of type bit.

 

z <=d0 when sel1 = '0' and sel0 = '0' else d1 when sel1 = '0' and sel0 = '1' else d2 when sel1 = '1' and sel0 = '0' else d3 when sel1 = '1' and sel0 = '1';

 

The statement is sensitive to all of the signals mentioned in the expressions and the conditions on the right of the assignment arrow.  So whenever any of these change value, the conditional assignment is reevaluated and a new transaction scheduled on the driver for the target signal.

If we look more closely at the multiplexer model, we note that the last condition

is redundant, since the signals sel0 and sel1 are of type bit If none of the previous conditions are true, the signal should always be assigned the last waveform So we can rewrite the example as:

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z <=d0 when sel1 = '0' and sel0 = '0' else d1 when sel1 = '0' and sel0 = '1' else d2 when sel1 = '1' and sel0 = '0' else d3;

 

A very common case in function modeling is to write a conditional signal assign- ment with no conditions, as in the following example:

 

PC_incr : next_PC <= PC + 4 after 5 ns;

 

 

 

 

 

 

 

 

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