VHDL Tutorial

Assertion statements in VHDL

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Assertion Statements


One of the reasons for writing models of computer systems is to verify that a design functions  correctly We  can  partially  test  a  model  by  applying  sample  inputs  and checking that the outputs meet our expectations.   If they do not, we are then faced with  the  task  of  determining  what  went  wrong  inside  the  design This  task  can  be made  easier  using  assertion statements  that  check  that  expected  conditions  are  met within the model.   An assertion statement is a sequential statement, so it can be in- cluded anywhere in a process body.   The syntax rule for an assertion statement is


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assert boolean_expression

[ report expression ] [ severity expression ] ;


The  simplest  form  of  assertion  statement  just  includes  the  keyword  assert  fol- lowed by a Boolean expression that we expect to be true when the assertion state- ment is executed.   If the condition is not met, we say that an assertion violation has occurred If an assertion violation arises during simulation of a model, the simulator reports the fact.   For example, if we write


assert initial_value <= max_value;


and initial_value is larger than max_value when the statement is executed during sim- ulation, the simulator will let us know.

We can get the simulator to provide extra information by including a report clause in an assertion statement, for example:


assert initial_value <= max_value

report "initial value too large";


The string that we provide is used to form part of the assertion violation message. VHDL predefines an enumeration type severity_level, defined as


type severity_level is (note, warning, error, failure);


We can include a value of this type in a severity clause of an assertion statement.  This value indicates the degree to which the violation of the assertion affects operation of the model.   Some example are:


assert packet_length /= 0

report "empty network packet received"

severity warning;

assert clock_pulse_width >= min_clock_width

severity error;


If we omit the report clause, the default string in the error message is “Assertion violation If we omit the severity clause, the default value is error.  The severity value

is usually used by a simulator to determine whether or not to continue execution after an assertion violation.   Most simulators allow the user to specify a severity threshold, beyond which execution is stopped.




An  important  use  for  assertion  statements  is  in  checking  timing  constraints that apply to a model.  For example, in an edge-triggered register, when the clock changes from ‘0’ to ‘1’, the data input is sampled, stored and transmitted through

to the output.   Let us suppose that the clock input must remain at ‘1’ for at least

5 ns.   Figure 3-8  is  a  model  for  a  register  that  includes  a  check  for  legal  clock pulse width.




entity edge_triggered_register is

port ( clock : in bit;

d_in : in real;  d_out : out real );

end entity edge_triggered_register;


architecture check_timing of edge_triggered_register is begin

store_and_check : process (clock) is variable stored_value : real; variable pulse_start : time;


case clock is when '1' =>

pulse_start := now;

stored_value := d_in;

d_out <= stored_value;

when '0' =>

assert now = 0 ns or (now – pulse_start) >= 5 ns

report "clock pulse too short";

end case;

end process store_and_check;

end architecture check_timing;


An entity and architecture body for an edge-triggered register, including a timing check for correct

pulse width on the clock input.


The architecture body contains a process that is sensitive to changes on the clock input.   When the clock changes from ‘0’ to ‘1’, the input is stored, and the current simulation time, accessed using the predefined function now, is recorded

in the variable pulse_start When the clock changes from ‘1’ to ‘0’, the difference between pulse_start and the current simulation time is checked by the assertion