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VHDL Tutorial |
Architecture bodies in VHDL | ||
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Introduction Fundamental concepts Modelling concepts Elements of behaviour Elements of structure Analysis elaboration Lexical elements Identifiers Numbers Characters and strings Syntax descriptions Constants and variables Scalar type Integer types Floating point types Time type Enumeration types Character types Boolean type Bits type Standard logic Sequential statements Case statements Loop and exit statements Assertion statements Array types & array operations Architecture bodies Entity declarations Behavioral descriptions Wait statements Delta delays Process statements Conditional signal assignment Selected signal assigment Structural descriptions Library and library clauses Procedures Procedure parameters Signal parameters Default values Unconstrained array parameter Functions Package declarations and bodies Subprograms in package Use clauses Resolved signals and subtypes Resolved signals and ports Parameterizing behavior Parameterizing structure
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Architecture Bodies
The internal operation of a module is described by an architecture body. An archi- tecture body generally applies some operations to values on input ports, generating values to be assigned to output ports. The operations can be described either by pro- cesses, which contain sequential statements operating on values, or by a collection of components representing sub-circuits. Where the operation requires generation of in- termediate values, these can be described using signals, analogous to the internal wires of a module. The syntax rule for architecture bodies shows the general outline:
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architecture_body ⇐ architecture identifier of entity_name is { block_declarative_item } begin { concurrent_statement } end [ architecture ] [ identifier ] ;
The identifier names this particular architecture body, and the entity name speci- fies which module has its operation described by this architecture body. If the iden- tifier is included at the end of the architecture body, it must repeat the name of the architecture body. There may be several different architecture bodies corresponding to a single entity, each describing an alternative way of implementing the module’s operation. The block declarative items in an architecture body are declarations need- ed to implement the operations. The items may include type and constant declara- tions, signal declarations and other kinds of declarations that we will look at in later chapters. The concurrent statements in an architecture body describe the module’s opera- tion. One form of concurrent statement, which we have already seen, is a process statement. We have looked at processes first because they are the most fundamental form of concurrent statement. All other forms can ultimately be reduced to one or more processes. Concurrent statements are so called because conceptually they can be activated and perform their actions together, that is, concurrently. Contrast this with the sequential statements inside a process, which are executed one after another. Concurrency is useful for modeling the way real circuits behave. When we need to provide internal signals in an architecture body, we must define them using signal declarations. The syntax for a signal declaration is very similar to that for a variable declaration:
signal_declaration ⇐ signal identifier { , … } : subtype_indication [ := expression ] ; This declaration simply names each signal, specifies its type and optionally includes an initial value for all signals declared by the declaration. An important point that we mentioned earlier is that the ports of the entity are also visible to processes inside the architecture body and are used in the same way as signals. This corresponds to our view of ports as external pins of a circuit: from the internal point of view, a pin is just a wire with an external connection. So it makes sense for VHDL to treat ports like signals inside an architecture of the entity.
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