VHDL Tutorial

Analysis elaboration and execution
Fundamental concepts
Modelling concepts
Elements of behaviour
Elements of structure
Analysis elaboration

Lexical elements
Characters and strings 
Syntax descriptions
Constants and variables
Scalar type
Integer types
Floating point types
Time type
Enumeration types
Character types
Boolean type 
Bits type
Standard logic
Sequential statements
Case statements
Loop and exit statements
Assertion statements
Array types & array operations
Architecture bodies
Entity declarations
Behavioral descriptions 
Wait statements
Delta delays
Process statements
Conditional signal assignment 
Selected signal assigment
Structural descriptions
Library and library clauses
Procedure parameters
Signal parameters
Default values
Unconstrained array parameter
Package declarations and bodies
Subprograms in package
Use clauses
Resolved signals and subtypes
Resolved signals and ports
Parameterizing behavior
Parameterizing structure


Analysis, Elaboration and Execution


One of the main reasons for writing a model of a system is to enable us to simulate

it.  This involves three stages: analysis, elaboration and execution.  Analysis and elab- oration are also required in preparation for other uses of the model, such as logic syn- thesis.

In the first stage, analysis, the VHDL description of a system is checked for various kinds of errors.  Like most programming languages, VHDL has rigidly defined syntax and semantics The syntax is the set of grammatical rules that govern how a model

is written.  The rules of semantics govern the meaning of a program.  For example, it makes sense to perform an addition operation on two numbers but not on two pro- cesses.

During the analysis phase, the VHDL description is examined, and syntactic and static semantic errors are located.  The whole model of a system need not be analyzed

at once.  Instead, it is possible to analyze design units, such as entity and architecture body declarations, separately.  If the analyzer finds no errors in a design unit, it creates an intermediate representation of the unit and stores it in a library.   The exact mech- anism varies between VHDL tools.

The second stage in simulating a model, elaboration, is the act of working through the design hierarchy and creating all of the objects defined in declarations.   The ulti- mate product of design elaboration is a collection of signals and processes, with each process possibly containing variables.   A model must be reducible to a collection of signals and processes in order to simulate it.

The third stage of simulation is the execution of the model.  The passage of time

is simulated in discrete steps, depending on when events occur.  Hence the term dis- crete event simulation is used.  At some simulation time, a process may be stimulated by changing the value on a signal to which it is sensitive.  The process is resumed and may schedule new values to be given to signals at some later simulated time.  This is called scheduling a transaction on that signal.   If the new value is different from the

previous value on the signal, an event occurs, and other processes sensitive to the sig- nal may be resumed.

The simulation starts with an initialization phase, followed by repetitive execu- tion of a simulation cycle.  During the initialization phase, each signal is given an ini- tial value, depending on its type.  The simulation time is set to zero, then each process instance is activated and its sequential statements executed Usually, a process will include a signal assignment statement to schedule a transaction on a signal at some later simulation time Execution of a process continues until it reaches a wait state- ment, which causes the process to be suspended.

During the simulation cycle, the simulation time is first advanced to the next time

at which a transaction on a signal has been scheduled.   Second, all the transactions scheduled for that time are performed.  This may cause some events to occur on some signals Third,  all  processes  that  are  sensitive  to  those  events  are  resumed  and  are allowed to continue until they reach a wait statement and suspend.   Again, the pro- cesses usually execute signal assignments to schedule further transactions on signals. When all the processes have suspended again, the simulation cycle is repeated.  When the simulation gets to the stage where there are no further transactions scheduled, it stops, since the simulation is then complete.

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