Design Of Two Stage OPAMP 

CMOS Introduction CMOS Amplifier Amplifier characteristics Gain Output dynamic range Bandwidth and rise time Settling time and aberrations Slew rate Noise Efficiency Linearity Electronic amplifiers TwoStage Amplifier Design Of OPAMP Design Of Two Stage OPAMP

This design procedure assumes that the gain at dc (A_{v}), unitygain bandwidth (GB), Input common –mode range[V_{in}(min) and V_{in}(max)], Load capacitance(C_{L}),slew rate(SR),Settling Time(T_{s}),Output voltage swing[V_{out}(max) and V_{out}(min)],and Power dissipation(P_{diss}) are given.
1. The smallest device length that will keep the channel modulation parameter constant and give good matching for current mirrors has been chosen. 2. From the desired phase margin, the minimum value for C_{c }is chosen ,that is ,for a 60^{0 }phase margin we have used the following relationship. This assumes that z>=10GB. C_{c}>0.22 C_{L} 3. The minimum value for the “tail current” (I_{5}) from the largest of the two values is determined. I_{5}=SR.C_{C } _{ } I_{5} nearly equal to 10(V_{DD}+V_{ss}) /(2T_{S}) 4. .Design for S_{3} from the maximum input voltage specification. S_{3}=2I_{3}/(K’_{3}[V_{DD}] V_{in}(max) V_{T03}(max)+ V_{T1}(min)]^{2 }>=1 5. The pole and zero due to C_{gs3} and C_{gs4 }(=0.67W_{3L3 }C_{ox}) will not be dominant by assuming p_{3} to be greater than 10GB. g_{m3}/2C_{gs3}>10GB 6. Design for S_{1 }(S_{2}) to achieve desired GB. g_{m1=}GB.C_{C }=> S_{1}= S_{2}=g_{m2}/K’_{2}I_{5}
7. Design for S_{5} from the minimum input voltage. First we have calculated V_{DS5}(sat) and then we have find S_{5}. V_{DS5}(sat)= V_{in}(min) V_{ss}( I_{5}/β_{1})^{1/2} V_{T1}(max)>=100mV S_{5}=2I_{5}/ K’_{5}[V_{DD}(sat)]^{2} 8. Find S_{6} and I_{6} by letting the second pole(p_{2}) be equal to 2.2 times GB. g_{m6}=2.2 g_{m2}(C_{L}/C_{C}) Let V_{SG4}= V_{SG6}, which gives S_{6}= S_{4} g_{m6}/ g_{m4} Knowing g_{m6} and S_{6 }allows us to solve for I_{6} as I_{6}= g^{2}_{m6g }/2k’_{6 }S_{ 6.} 1. Alternately, I_{6} can be calculated by solving for S_{6 } using S_{6}= g_{m6}/K’_{6}V_{DS6}(sat) And then using the previous relationship to find I_{6.}The proper mirror between M3 and M4 is no longer guaranteed.
2. Design _{.} S_{7} to achieve the desired current ratios between I_{5} and I_{6.} S_{7}= (I_{5} /I_{6}).S_{5} 3. Check gain and power dissipation specifications. 4. By simulating the circuit we have seen that all the specifications are met
· Now let us consider an example:
The circuit is given below. Design an amplifier similar to the figure given below that meets the following specifications with a phase margin of 60^{0}. Assuming channel length to be 1um. A_{v}>5000V/V V_{DD}=2.5 V V_{SS}=2.5 GB=5MHz C_{L}=10pF SR>10V/us V_{out }range=(+)2V ICMR=1 to 2 V P_{diss}=≤2mW
SOLUTION: · To calculate the minimum value of the compensation capacitor C_{C } , i.e., C_{C}>(2.2/10)(10pF) Now choosing C_{C }as 3pF. · Using SLEW RATE specification and C_{C} we will calculate I_{5} I_{5}=30uA · Now calculating (W/L)_{3}=15 Therefore, (W/L)_{3}=(W/L)_{4} · Now checking the value of mirror pole,p_{3},to make sure it is greater than 10GB. We assume C_{0x}=2.47fF/um^{2} P_{3}=g_{m3}/2C_{gs3}=2.81*10^{9} rad/s Or 448 MHz. Here p_{3}and z_{3} are not of concern (as P_{3}>>10GB)
· Next we have to calculate g_{m1}. g_{m1}=94.25us
Therefore,(W/L)_{1}=2.79≈3.0 · Now we will calculate V_{DS5}=0.35 Now we will find out (W/L)_{5}=4.5 We know that, g_{m6 }≥ 10g_{m1 }≥ 942.5 us (g_{m4}=150 us) · S_{6}=S_{4}(g_{m6}/_{ }g_{m4})=94 · Now calculating I_{6} we get I_{6}≈95 uA. Designing the circuit as such that we get S_{6}=15. · Now we will finally calculate (W/L)_{7} (W/L)_{7}=14.25≈14
· The value of V_{out }(min) is V_{min }(out)=V_{DS7}(sat)=0.371 V This is less than required. At this point 1^{st} cut design is complete. · The power dissipation can be calculated as P_{diss}=0.625 mW.
Now we have to check that whether the gain specification is met. A_{V}=[(2(92.45*10^{6})(942.5*10^{6}))]/[(30*10^{6 }(0.04+0.05)95*10^{6}(0.04+0.05))] This meets specifications.
To increase the gain the easiest way is to increase W and L value by factor 2, which because of the decreased value of λ would increase the gain by a factor of 20.
Future plans In future circuit need to be simulated and check what happens when the channel length is decreased. Limitations: If the channel length is being decreased the speed increases but after a specific length the channel length can’t be decreased. Applications: Opamps are among the most widely used electronic devices today, being used in a vast array of consumer, industrial, and scientific devices. The application of a two stage opamp is very wide spread. Places where a high input impedance and low output impedance is required Two stage OPAMPs are suitably used.
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