Design Of Two Stage OP-AMP Contents CMOS Introduction CMOS Amplifier Amplifier characteristics Gain Output dynamic range Bandwidth and rise time Settling time and aberrations Slew rate Noise Efficiency Linearity Electronic amplifiers Two-Stage Amplifier Design  Of  OP-AMP Design Of Two Stage OP-AMP Watch the latest videos on YouTube.com This design procedure assumes that the gain at dc (Av), unity-gain bandwidth (GB), Input common –mode range[Vin(min) and Vin(max)], Load capacitance(CL),slew rate(SR),Settling Time(Ts),Output voltage swing[Vout(max) and Vout(min)],and Power dissipation(Pdiss) are given.   1.      The smallest device length that will keep the channel modulation parameter constant and give good matching for current mirrors has been chosen. 2.     From the desired phase margin, the minimum value for Cc  is chosen ,that is ,for a 600 phase margin we have used the following relationship.                This assumes that  z>=10GB.                     Cc>0.22 CL 3.      The minimum value for the “tail current” (I5)   from the largest of the two values is determined.        I5=SR.CC                                                                                           I5 nearly equal to 10(VDD+|Vss|) /(2TS) 4.       .Design for S3 from the maximum input voltage                                                                                                                        specification. S3=2I3/(K’3[VDD]- Vin(max)- |VT03|(max)+ VT1(min)]2 >=1 5.                                             The pole and zero due to Cgs3 and Cgs4 (=0.67W3L3 Cox) will not be dominant by assuming p3 to be greater than 10GB.                   gm3/2Cgs3>10GB                                                                        6.  Design for S1 (S2) to achieve desired GB.     gm1=GB.CC    =>  S1= S2=gm2/K’2I5   7.  Design for S5 from the minimum input voltage. First we have calculated VDS5(sat) and then we have find S5. VDS5(sat)= Vin(min)- Vss-( I5/β1)1/2- VT1(max)>=100mV S5=2I5/ K’5[VDD(sat)]2 8.  Find S6 and I6 by letting the second pole(p2) be equal to 2.2 times GB. gm6=2.2 gm2(CL/CC) Let VSG4= VSG6, which gives S6= S4 gm6/ gm4 Knowing gm6 and S6 allows us to solve for I6 as I6= g2m6g /2k’6 S 6. 1.    Alternately, I6 can be calculated by solving for S6 using S6= gm6/K’6VDS6(sat) And then using the previous relationship to find I6.The proper mirror between M3 and M4 is no longer guaranteed.   2.    Design . S7 to achieve the desired current ratios between I5 and I6. S7= (I5 /I6).S5 3.    Check gain and power dissipation specifications. 4.  By simulating the circuit we have seen that all the specifications are met     ·                         Now let us consider an example:   The circuit is given below. Design an amplifier similar to the figure given below that meets the following specifications with a phase margin of 600. Assuming channel length to be 1um. Av>5000V/V             VDD=2.5 V VSS=-2.5                  GB=5MHz CL=10pF                  SR>10V/us Vout range=(+-)2V    ICMR=-1 to 2 V Pdiss=≤2mW   SOLUTION: ·                         To calculate the minimum value of the compensation capacitor CC , i.e.,       CC>(2.2/10)(10pF)       Now choosing CC as 3pF. ·                         Using SLEW RATE specification and CC we will calculate I5        I5=30uA ·                         Now calculating (W/L)3=15             Therefore,              (W/L)3=(W/L)4 ·                         Now checking the value of mirror pole,p3,to make sure it is greater than 10GB. We assume C0x=2.47fF/um2               P3=-gm3/2Cgs3=2.81*109   rad/s               Or 448 MHz. Here p3and z3 are not of concern                    (as P3>>10GB)   ·                         Next we have to calculate gm1.   gm1=94.25us                 Therefore,(W/L)1=2.79≈3.0 ·                         Now we will calculate VDS5=0.35               Now we will find out (W/L)5=4.5               We know that,   gm6 ≥ 10gm1 ≥ 942.5 us                (gm4=150 us) ·                         S6=S4(gm6/ gm4)=94 ·                         Now calculating I6 we get              I6≈95 uA. Designing the circuit as such that we get S6=15. ·                          Now we will finally calculate (W/L)7 (W/L)7=14.25≈14   ·                          The value of Vout (min) is                Vmin (out)=VDS7(sat)=0.371 V This is less than required. At this point 1st cut design is complete. ·                          The power dissipation can be calculated as               Pdiss=0.625 mW.   Now we have to check that whether the gain specification is met. AV=[(2(92.45*10-6)(942.5*10-6))]/[(30*10-6 (0.04+0.05)95*10-6(0.04+0.05))] This meets specifications.   To increase the gain the easiest way is to increase W and L value by factor 2, which because of the decreased value of λ would increase the gain by a factor of 20.   Future plans In future   circuit need to be simulated and check what happens when the channel length is decreased. Limitations: If the channel length is being decreased the speed increases but after a specific length the channel length can’t be decreased. Applications: Op-amps are among the most widely used electronic devices today, being used in a vast array of consumer, industrial, and scientific devices. The application of a two stage op-amp is very wide spread. Places where a high input impedance and low output impedance is required Two stage OPAMPs are suitably used.   Home     `The contents of this webpage are copyrighted © 2008 www.freehost7.com` ` All Rights Reserved.`