Enhanced RISC

 

 

Many existing RISC architectures require larger code size to perform a given task with the traditional CISC (Complex Instruction Set Computer) architectures. RISC MCU’s are often chosen where a high speed is needed. The reduced instruction set will be fast, but reduced in complexity. The AVR is designed to be a RISC MCU with a larger number of instructions to reduce the code size and to increase the speed further. Ciscy-like instructions are introduced without letting the RISC performance and low power consumption features suffer. This first major enhancement was made after thorough analysis of several architectures and large amounts of application code. Still, the regular AVR RISC architecture enables cost effective implementations. The second enhancement is achieved by tuning the architecture for optimizing code generation for the C language. This was done with a large application oriented benchmark suite, where the code was pseudo-compiled for the different enhancement alternatives in the architecture. Special tuning of the different addressing modes was important, “need to have” instead of “nice to have”. Many MCU architectures have only a small number of general registers or working registers (accumulators) - typically 1-8 registers. This is a major drawback for the C compiler design, where a lot of data moving is necessary. The AVR has 32 general-purpose working registers, that the C compiler fully utilizes to achieve the highest code density.

 
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